| US 7,525,138 B2 | ||
| JFET device with improved off-state leakage current and method of fabrication | ||
| Samar K. Saha, Milpitas, Calif. (US); and Ashok K. Kapoor, Palo Alto, Calif. (US) | ||
| Assigned to DSM Solutions, Inc., Los Gatos, Calif. (US) | ||
| Filed on May 03, 2007, as Appl. No. 11/744,080. | ||
| Prior Publication US 2008/0272402 A1, Nov. 06, 2008 | ||
| Int. Cl. H01L 29/80 (2006.01); H01L 31/112 (2006.01) | ||
| U.S. Cl. 257—285 [257/286; 257/E27.069; 257/E29.057] | 21 Claims |
| 1. A junction field effect transistor, comprising:
a semiconductor substrate;
a first impurity region of a first conductivity type which is formed in the substrate;
a second impurity region of the first conductivity type which is formed in the substrate and spaced apart from the first impurity
region;
a channel region of the first conductivity type which is formed between the first and second impurity regions;
a gate region of a second conductivity type formed in the substrate between the first and second impurity regions;
a first link region of the first conductivity type formed in the substrate between the first impurity region and the gate
region, wherein the first link region has a different junction profile than the first impurity region; and
a gap region formed in the substrate between the gate region and the first link region such that the first link region is
spaced apart from the gate region, wherein the gap region has a lower doping concentration than the channel region and the
first impurity region.
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