| US 7,525,137 B2 | ||
| TFT mask ROM and method for making same | ||
| Andrew J. Walker, Mountain View, Calif. (US); and Christopher Petti, Mountain View, Calif. (US) | ||
| Assigned to Sandisk Corporation, Sunnyvale, Calif. (US) | ||
| Filed on Jul. 12, 2006, as Appl. No. 11/484,757. | ||
| Application 11/484757 is a division of application No. 10/965780, filed on Oct. 18, 2004, granted, now 7,250,646. | ||
| Application 10/965780 is a division of application No. 09/983988, filed on Oct. 26, 2001, granted, now 6,841,813. | ||
| Application 09/983988 is a continuation in part of application No. 09/961278, filed on Sep. 25, 2001, granted, now 6,593,624. | ||
| Application 09/961278 is a continuation in part of application No. 09/927648, filed on Aug. 13, 2001, granted, now 6,881,994. | ||
| Prior Publication US 2006/0249735 A1, Nov. 09, 2006 | ||
| Int. Cl. H01L 29/772 (2006.01) | ||
| U.S. Cl. 257—278 [257/7; 257/74; 257/390; 257/E21.571] | 11 Claims |
| 1. A TFT mask ROM array, comprising:
a first plurality of spaced apart conductor rails disposed at a first height above a substrate in a first direction;
a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first
direction, each rail stack including:
a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductor rails;
a conductive film; and
a gate insulating film disposed between a second surface of the first semiconductor layer and the conductive film;
wherein TFTs are formed at intersections of two adjacent conductor rails and one rail stack; and
wherein the TFTs comprise a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
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