| US 7,525,136 B2 | ||
| JFET device with virtual source and drain link regions and method of fabrication | ||
| Samar K. Saha, Milpitas, Calif. (US); and Ashok K. Kapoor, Palo Alto, Calif. (US) | ||
| Assigned to DSM Solutions, Inc., Los Gatos, Calif. (US) | ||
| Filed on May 03, 2007, as Appl. No. 11/744,120. | ||
| Prior Publication US 2008/0272403 A1, Nov. 06, 2008 | ||
| Int. Cl. H01L 29/80 (2006.01); H01L 31/112 (2006.01) | ||
| U.S. Cl. 257—270 [257/272; 257/E27.069] | 14 Claims |
| 1. A junction field effect transistor, comprising:
a semiconductor substrate;
a source region of a first conductivity type which is formed in the substrate;
a drain region of the first conductivity type which is formed in the substrate;
a channel region of the first conductivity type which is formed in the substrate;
a gate region of a second conductivity type formed in the substrate between the source and drain regions;
a first virtual link region formed in the substrate between the gate region and either the source region or the drain region;
a dielectric material which overlays the first virtual link region; and
a first electrode region which overlays the dielectric material;
wherein the first electrode region is operable to receive a bias voltage such that an inversion layer of impurities of the
first conductivity type forms in the first virtual link region.
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