| US 7,525,120 B2 | ||
| Thin film transistor array substrate and method of fabricating the same | ||
| Kyoung Mook Lee, Seoul (Korea, Republic of); Seung Hee Nam, Kyounggi-do (Korea, Republic of); and Jae Young Oh, Kyounggi-do (Korea, Republic of) | ||
| Assigned to LG Display Co., Ltd., Seoul (Korea, Republic of) | ||
| Filed on Mar. 12, 2007, as Appl. No. 11/716,690. | ||
| Application 11/716690 is a division of application No. 10/833185, filed on Apr. 28, 2004, granted, now 7,217,586. | ||
| Claims priority of application No. 10-2003-28642 (KR), filed on May 06, 2003. | ||
| Prior Publication US 2007/0170432 A1, Jul. 26, 2007 | ||
| Int. Cl. H01L 29/04 (2006.01) | ||
| U.S. Cl. 257—59 [257/66; 257/72; 257/E29.291; 257/E29.294] | 13 Claims |
| 1. A thin film transistor array substrate, comprising:
a gate line formed on a substrate;
a data line formed on the substrate intersecting with the gate line to define a pixel region;
a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate
electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor
layer formed on the gate insulating layer, an ohmic contact layer on the semiconductor layer, and a source electrode and a
drain electrode on the ohmic contact layer; and
a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor,
wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode
material, and covering the gate line,
wherein the transparent electrode material contacts the gate insulating layer, and
wherein the transparent electrode material directly contacts a side portion of the semiconductor layer.
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