| US 7,524,731 B2 | ||
| Process of forming an electronic device including an inductor | ||
| James Jen-Ho Wang, Phoenix, Ariz. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Sep. 29, 2006, as Appl. No. 11/540,614. | ||
| Prior Publication US 2008/0079115 A1, Apr. 03, 2008 | ||
| Int. Cl. H01L 21/20 (2006.01) | ||
| U.S. Cl. 438—381 [438/622; 257/531; 257/E21.022] | 20 Claims |
| 1. A process of forming an electronic device comprising:
forming an interconnect level overlying a die substrate, wherein the interconnect level comprises a first interconnect and
a second interconnect;
forming a shock-absorbing layer overlying the interconnect level;
patterning the shock-absorbing layer to define a first opening that exposes the first interconnect and a second opening that
exposes the second interconnect;
forming conductive traces, wherein:
the conductive traces include a first conductive trace and a second conductive trace;
a via portion of the first conductive trace extends to the first opening of the shock-absorbing layer and is electrically
connected to the first interconnect, and a primary pad portion of the first conductive trace overlies the shock-absorbing
layer; and
a secondary pad portion of the second conductive trace overlies the shock-absorbing layer, and a via portion of the second
conductive trace extends to the second opening of the shock-absorbing layer and is electrically connected to the second interconnect;
and
attaching at least one wire to the conductive traces to form an inductor, wherein:
a first wire of the at least one wire is attached to the primary pad portion of the first conductive trace; and
the first wire or a second wire of the at least one wire is attached to the secondary pad portion of the second conductive
trace.
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