| US 7,524,716 B2 | ||
| Fabricating method of semiconductor structure | ||
| Shyh-Fann Ting, Gangshan Township, Kaohsiung County (Taiwan); Cheng-Tung Huang, Kaohsiung (Taiwan); Wen-Han Hung, Kaohsiung (Taiwan); Li-Shian Jeng, Taitung (Taiwan); Kun-Hsien Lee, Tainan (Taiwan); Tzyy-Ming Cheng, Hsinchu (Taiwan); Jing-Chang Wu, Douliou (Taiwan); and Tzermin Shen, Hsinchu (Taiwan) | ||
| Assigned to United Microelectronics Corp., Hsinchu (Taiwan) | ||
| Filed on May 30, 2007, as Appl. No. 11/755,669. | ||
| Application 11/755669 is a division of application No. 11/399827, filed on Apr. 07, 2006, granted, now 7,288,822. | ||
| Prior Publication US 2007/0238241 A1, Oct. 11, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—197 [438/199; 438/231; 438/300; 257/E21.585] | 8 Claims |
| 1. A method for fabricating a semiconductor structure, comprising:
providing a substrate that has therein a first well of a first conductivity type and a second well of a second conductivity
type;
forming a first gate structure on the second well;
removing a portion of the substrate beside the first gate structure to form a first opening;
performing a first epitaxy process with a first mixed gas to form in the first opening a first strained layer comprising silicon
and a first IV-group element, wherein the first mixed gas comprises a first gas containing silicon and a second gas containing
the first IV-group element and the percentage of the second gas in the first mixed gas is increased with time during the first
epitaxy process; and
forming a MOS transistor of the second conductivity type on the first well, comprising:
forming a second gate structure on the first well;
removing a portion of the substrate beside the second gate to form a second opening; and
forming a source/drain region of the second conductivity type in the first well around and under the second opening.
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