| US 7,524,706 B2 | ||
| Method of fabricating a thin film transistor array panel | ||
| Je Hun Lee, Seoul (Korea, Republic of); Yang Ho Bae, Suwon-si (Korea, Republic of); Beom Seok Cho, Seoul (Korea, Republic of); and Chang Oh Jeong, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Aug. 24, 2007, as Appl. No. 11/844,597. | ||
| Application 11/844597 is a division of application No. 11/234470, filed on Sep. 23, 2005, granted, now 7,276,732. | ||
| Claims priority of application No. 10-2004-0076813 (KR), filed on Sep. 24, 2004. | ||
| Prior Publication US 2008/0038885 A1, Feb. 14, 2008 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—149 [438/151; 438/685] | 10 Claims |
| 1. A method of fabricating a thin film transistor array panel comprising:
forming a gate line on a substrate;
forming a gate insulating layer on the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a
Mo alloy and the second conductive layer containing Cu, and
performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer.
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