| US 5,974,526 C1 (6786th) | ||
| SUPERSCALAR RISC INSTRUCTION SCHEDULING | ||
| Sanjiv Garg, Freemont, Calif.; Kevin Ray Iadonato, San Jose, Calif.; Le Trong Nguyen, Sereno, Calif., and Johannes Wang, Redwood City, Calif., assignors to Transmeta Corporation, Santa Clara, Calif. | ||
| Reexamination Request No. 90/008,712, Jun. 11, 2007. | ||
| Reexamination Certificate for Patent 5,974,526, issued Oct. 26, 1999, Appl. No. 990,414, Dec. 15, 1997. | ||
| Continuation of application No. 08/594,401, filed on Jan. 31, 1996, now Pat. No. 5,737,624, and a continuation of application No. 08/219,425, filed on Mar. 29, 1994, now Pat. No. 5,497,499, and a continuation of application No. 07/860,719, filed on Mar. 31, 1992, now abandoned. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 9/38;9/30 (2006.01) | ||
| U.S. Cl. 712—23 |
| AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT: |
| The patentability of claims 1-34 is confirmed. |
| 1. In a computer system having a register file comprising a plurality of registers and a plurality of index-addressable temporary storage locations, a method for executing instructions having a prescribed program order, comprising the steps of: (1) storing a plurality of instructions in an instruction buffer, wherein each instruction has an input and an output;
(2) assigning a unique one of the plurality of index-addressable temporary storage locations to each one of said plurality of instructions in said instruction buffer, wherein an output corresponding to a given one of said plurality of instructions is stored in said index-addressable temporary storage location assigned to said given one of said plurality of instructions;
(3) determining whether one of said plurality of instructions in said instruction buffer is a dependent instruction, wherein said dependent instruction has an input that is an output of a previous instruction, wherein said previous instruction is an instruction in said instruction buffer that precedes said dependent instruction in the prescribed program order; and
(4) associating said index-addressable temporary storage location assigned to said previous instruction with said input.
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