US 5,737,624 C1 (6784th)
SUPERSCALAR RISC INSTRUCTION SCHEDULING
Sanjiv Garg, Freemont, Calif.; Kevin Ray Iadonato, San Jose, Calif.; Le Trong Nguyen, Monte Sereno, Calif., and Johannes Wang, Redwood City, Calif., assignors to Transmeta Corporation, Santa Clara, Calif.
Reexamination Request No. 90/008,691, Jun. 11, 2007.
Reexamination Certificate for Patent 5,737,624, issued Apr. 7, 1998, Appl. No. 594,401, Jan. 31, 1996.
Continuation of application No. 08/219,425, filed on Mar. 29, 1994, now Pat. No. 5,497,499, which is a continuation of application No. 07/860,719, filed on Mar. 31, 1992, now abandoned.
Int. Cl. G06F 9/38 (2006.01)
U.S. Cl. 712—23
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
The patentability of claims 1-19 is confirmed.
1. A system for register renaming in a computer system capable of out-of-order instruction execution, comprising:
a temporary buffer comprising a plurality of storage locations for storing execution results, wherein an execution result for an instruction is stored at one of said plurality of storage locations, said one of a plurality of storage locations being determined by a location of said instruction in an instruction window;
tag assignment logic for receiving data dependency results from a data dependency checker and for outputting a tag in place of a register address for an operand of a first instruction if said first instruction is dependent on a previous one of said plurality of instructions in said instruction window for said operand, wherein said tag represents an address of said operand in one of said plurality of storage locations.