| US 7,523,431 B2 | ||
| Semiconductor integrated circuit | ||
| Hiroshi Yajima, Sagamihara (Japan); and Kaoru Ishida, Shijyonawate (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Feb. 11, 2005, as Appl. No. 11/55,085. | ||
| Claims priority of application No. 2004-042428 (JP), filed on Feb. 19, 2004. | ||
| Prior Publication US 2005/0186934 A1, Aug. 25, 2005 | ||
| Int. Cl. G06F 9/455 (2006.01); G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—11 | 2 Claims |
| 1. A semiconductor intergrated circuit comprising:
a semiconductor substrate having outer periphery;
a grounding terminal formed on said semiconductor substrate inside of said outer periphery of said semiconductor substrate;
a digital circuit block formed on said semiconductor substrate inside of said outer periphery of said semiconductor substrate;
an analog circuit block formed on said semiconductor substrate inside of said outer periphery of said semiconductor substrate;
a seal ring, formed at said outer periphery of said semiconductor substrate around said digital circuit block, said analog
cicruit block, and said grounding terminal, and adjacent to both said digital circuit block and said analog circuit block;
a first wiring pattern formed on said semiconductor substrate inside said outer periphery of said semiconductor substrate
and connected to said seal ring and said grounding terminal; and
a capacitor on said semiconductor substrate, said capacitor having a first end and a second end;
wherein said first wiring pattern includes: a second wiring pattern connected to the first end of said capacitor; and a third
wiring pattern connected to the second end of said capacitor and said grounding terminal.
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