| US 7,523,154 B2 | ||
| Write compensation circuit and signal interpolation circuit of recording device | ||
| Hirokuni Fujiyama, Osaka (Japan); Shiro Dosho, Osaka (Japan); Hiroyuki Nakahira, Kyoto (Japan); Akira Yamamoto, Osaka (Japan); and Hiroki Mouri, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Kadoma (Japan) | ||
| Filed on Aug. 08, 2005, as Appl. No. 11/198,950. | ||
| Application 11/198950 is a division of application No. 09/539206, filed on Mar. 30, 2000, granted, now 6,970,313. | ||
| Claims priority of application No. 11-94133 (JP), filed on Mar. 31, 1999; and application No. 11-342656 (JP), filed on Dec. 01, 1999. | ||
| Prior Publication US 2005/0270677 A1, Dec. 08, 2005 | ||
| Int. Cl. G06G 7/00 (2006.01) | ||
| U.S. Cl. 708—801 | 5 Claims |
| 1. A signal interpolation circuit wherein a pair of input signals having different phases are split into a pair of output
signals having a phase similar to that of the pair of input signals, respectively, and an output signal having a phase intermediate
between the phases of the pair of output signals; and by comprising a plurality of elements, the pair of output signals and
the output signal having the intermediate phase have substantially the same propagation speed,
the signal interpolation circuit further comprising:
a control section for controlling the propagation speed.
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