| US 7,522,083 B2 | ||
| Semiconductor device having D/A conversion portion | ||
| Ryusuke Sahara, Ome (Japan); Mitsugu Kusunoki, Kunitachi (Japan); Kazutaka Mori, Kokubunji (Japan); and Hiroshige Kogayu, Kokubunji (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Oct. 23, 2007, as Appl. No. 11/877,561. | ||
| Application 11/877561 is a division of application No. 11/409963, filed on Apr. 25, 2006, granted, now 7,310,266. | ||
| Claims priority of application No. 2005-128857 (JP), filed on Apr. 27, 2005. | ||
| Prior Publication US 2008/0055140 A1, Mar. 06, 2008 | ||
| Int. Cl. H03M 1/78 (2006.01) | ||
| U.S. Cl. 341—154 [341/144] | 6 Claims |

| 1. A semiconductor integrated circuit device comprising:
a signal line;
a segment D/A conversion portion having plural current source circuits;
first to third R2R D/A conversion portions each having plural current source circuits and an R2R ladder portion including a plurality of first resistors and a plurality second resistors, each of the plurality of second
resistors having a resistance value two times as large as a resistance value of each of the plurality of first resistors;
and
a trimming portion including the second and third R2R D/A conversion portions;
wherein the segment D/A conversion portion applies a first current, corresponding to a number of the plural current source
circuits which is determined by a first signal, to the signal line,
wherein the first R2R D/A conversion portion applies a second current, which varies in accordance with a second signal, to the signal line,
wherein the second R2R D/A conversion portion applies a third current, which varies in accordance with a first trimming signal, to the signal line,
and
wherein the third R2R D/A conversion portion applies a fourth current, which varies in accordance with a second trimming signal, to a first predetermined
node of the R2R ladder portion of the first R2R D/A conversion portion.
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