| US 7,521,969 B2 | ||
| Switch sequencing circuit systems and methods | ||
| Richard Booth, Riegelsville, Pa. (US); and Phillip Johnson, Hellertown, Pa. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Jul. 28, 2006, as Appl. No. 11/494,862. | ||
| Prior Publication US 2008/0024171 A1, Jan. 31, 2008 | ||
| Int. Cl. H03K 19/094 (2006.01) | ||
| U.S. Cl. 326—87 [326/68; 326/97] | 9 Claims |
| 1. An integrated circuit comprising:
a driver adapted to receive data signals and provide an output signal based on the data signals, wherein the driver comprises
a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the
output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal
based on the data signals; and
a sequencing circuit adapted to provide the data signals to the driver, wherein the sequencing circuit provides the data signals
with a selectable timing difference such that the first set of the plurality of transistors is switched on before the second
set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before
the first set of the plurality of transistors is switched off,
wherein the sequencing circuit further comprises:
a logic circuit adapted to receive a first complementary data signal, wherein the logic circuit comprises a first and a second
logic gate; and
a plurality of delay elements coupled to the logic circuit and adapted to provide the data signals as a second and third complementary
data signal based on the first complementary data signal.
|