| US 7,521,749 B2 | ||
| Nonvolatile semiconductor memory device including improved gate electrode | ||
| Fumitaka Arai, Yokohama (Japan); Yasuhiko Matsunaga, Kawasaki (Japan); Makoto Sakuma, Yokohama (Japan); Riichiro Shirota, Fujisawa (Japan); and Akira Shimizu, Oyama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 23, 2007, as Appl. No. 11/877,075. | ||
| Application 11/535514 is a division of application No. 11/118478, filed on May 02, 2005, granted, now 7,122,858. | ||
| Application 11/118478 is a division of application No. 10/648510, filed on Aug. 27, 2003, granted, now 7,078,763. | ||
| Application 11/877075 is a continuation of application No. 11/535514, filed on Sep. 27, 2006, granted, now 7,298,006. | ||
| Claims priority of application No. 2003-049615 (JP), filed on Feb. 26, 2003. | ||
| Prior Publication US 2008/0054340 A1, Mar. 06, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—316 [257/401; 257/E29.129; 257/E29.3; 365/185.05; 365/185.26] | 10 Claims |
| 1. A nonvolatile semiconductor memory device comprising:
a plurality of element isolation insulating films formed in a semiconductor substrate, each of the element isolation insulating
films being arranged in a predetermined interval and in a first direction, wherein the semiconductor substrate is divided
into a plurality of element regions by the element isolation insulating films;
first and second control gates being arranged in a predetermined interval and in a second direction perpendicular to the first
direction, each of the first and second control gates being intersected by the element isolation insulating films;
a floating gate formed on a gate insulating film formed on the element region between the first and second control gates;
and
an inter-gate insulating film which insulates the first and second control gates from the floating gate;
wherein the first and second control gates are formed above the element isolation insulating films, and
wherein a height of an upper surface of the element isolation insulating films on which the first and second control gates
are formed is lower than a height of an upper surface of the element isolation insulating films on which the first and second
control gates are not formed.
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