| US 7,521,711 B2 | ||
| Display device, method of production of the same, and projection type display device | ||
| Shingo Makimura, Kanagawa (Japan); Makoto Hashimoto, Kanagawa (Japan); Yoshiro Okawa, Kagoshima (Japan); Tomohiro Wada, Kumamoto (Japan); and Kazunori Kataoka, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan) | ||
| Filed on Oct. 14, 2005, as Appl. No. 11/251,430. | ||
| Application 11/251430 is a division of application No. 10/485790, filed on Feb. 04, 2004, granted, now 7,189,993. | ||
| Claims priority of application No. 2002-166380 (JP), filed on Jun. 07, 2002; and application No. PCT/JP03/07208 (WO), filed on Jun. 06, 2003. | ||
| Prior Publication US 2006/0033103 A1, Feb. 16, 2006 | ||
| Int. Cl. H01L 29/04 (2006.01) | ||
| U.S. Cl. 257—59 [257/65; 257/66] | 10 Claims |
| 1. A projection type display device emitting light of a light source to at least one display panel to project an image formed
by that display panel to a screen, wherein
said display panel comprises a substrate on which a display unit and a peripheral drive unit are integrally formed,
said display unit having pixels arranged in a matrix and pixel transistors integrally formed,
said drive unit having peripheral transistors of a drive circuit for scanning the matrix of the pixel transistors, and
both of said pixel transistors and peripheral transistor being thin film transistors comprising at least one polycrystalline
semiconductor thin film,
wherein an average crystal grain size of the polycrystalline semiconductor thin film of said pixel transistors and an average
crystal grain size of the polycrystalline semiconductor thin film of said peripheral transistors are different,
wherein the thickness of the polycrystalline silicon constituting the semiconductor thin film of said pixel transistors is
smaller than the thickness of the polycrystalline silicon constituting the semiconductor thin film of said peripheral transistors;
wherein the pixel transistors are formed with a first light shielding film between the pixel transistors and the substrate
and a second light shielding film formed above the pixel transistors; and
wherein source and drain interconnects formed over said pixel transistors function as a third light shielding film, and wherein
said second light shielding film is formed over said source and drain interconnects and is electrically connected to one of
said source and drain interconnects, and further comprising a substantially transparent pixel electrode formed over said second
light shielding film and electrically connected to said second light shielding film.
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