| US 7,521,380 B2 | ||
| Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors | ||
| Andrew M. Waite, Radebeul/Dresden (Germany); Scott Luning, Poughkeepsie, N.Y. (US); and Frank (Bin) Yang, Mahwah, N.J. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Apr. 23, 2007, as Appl. No. 11/738,828. | ||
| Prior Publication US 2008/0261408 A1, Oct. 23, 2008 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01) | ||
| U.S. Cl. 438—786 [438/792; 438/763; 257/E21.487; 257/E21.619] | 18 Claims |
| 1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate and a plurality of transistors formed on and in the semiconductor substrate, wherein the
plurality of transistors comprise narrow gate pitch transistors and wide gate pitch transistors, wherein narrow gate pitch
transistors each comprise a first gate electrode and the wide gate pitch transistors each comprise a second gate electrode,
and wherein adjacent ones of the first gate electrodes are spaced apart by a first distance, and wherein adjacent ones of
the second gate electrodes are spaced apart by a second distance greater than the first distance;
conformally depositing a first stress liner layer overlying the narrow gate pitch transistors, the wide gate pitch transistors
and the semiconductor layer;
conformally depositing an etch stop layer overlying the first stress liner layer, wherein the etch stop layer etches selectively
with respect to the first stress liner layer;
conformally depositing a second stress liner layer overlying the etch stop layer, wherein the second stress liner layer etches
selectively with respect to the etch stop layer; and
removing a portion of the second stress liner layer which overlies the narrow gate pitch transistors to expose an exposed
portion of the etch stop layer which overlies the narrow gate pitch transistor.
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