| US 7,521,358 B2 | ||
| Process integration scheme to lower overall dielectric constant in BEoL interconnect structures | ||
| Nicolas Bright, San Jose, Calif. (US); Dave Hemker, San Jose, Calif. (US); Fritz C. Redeker, Fremont, Calif. (US); and Yezdi Dordi, Palo Alto, Calif. (US) | ||
| Assigned to LAM Research Corporation, Freemont, Calif. (US) | ||
| Filed on Apr. 02, 2007, as Appl. No. 11/732,198. | ||
| Claims priority of provisional application 60/887279, filed on Dec. 26, 2006. | ||
| Prior Publication US 2008/0150138 A1, Jun. 26, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—637 [438/618; 438/598; 257/E21.495] | 25 Claims |
| 1. A method of fabricating an interconnect structure comprising:
forming a conductive line;
forming a first capping layer selectively over the conductive line and a dielectric layer;
forming a dielectric barrier layer over the dielectric layer and over the first capping layer;
forming a low-k layer over the first capping layer;
exposing the conductive line including
forming a mask layer having an opening over the low-k layer,
narrowing the opening in the mask layer, and
forming a via by extending the narrowed opening through the low-k layer at least to the first capping layer;
forming a first diffusion barrier layer on sidewalls of the via; and
filling the via with a first conductive material.
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