| US 7,521,300 B2 | ||
| Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate | ||
| Hajime Nagano, Yokohama (Japan); Takashi Yamada, Ebina (Japan); Tsutomu Sato, Yokohama (Japan); Ichiro Mizushima, Yokohama (Japan); and Hisato Oyamatsu, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 20, 2006, as Appl. No. 11/455,735. | ||
| Application 11/455735 is a division of application No. 10/237206, filed on Sep. 09, 2002, granted, now 7,187,035. | ||
| Claims priority of application No. 2001-293781 (JP), filed on Sep. 26, 2001. | ||
| Prior Publication US 2006/0234478 A1, Oct. 19, 2006 | ||
| Int. Cl. H01L 21/762 (2006.01) | ||
| U.S. Cl. 438—152 [438/164; 438/166; 257/E21.561] | 7 Claims |
| 1. A method of manufacturing a semiconductor device substrate, comprising:
forming a mask layer pattern above semiconductor layer insulated from a surface of a semiconductor substrate by an electrically
insulating layer;
etching the semiconductor layer in accordance with the pattern of the mask layer to form a trench exposing the insulting layer;
forming a protective layer on a side wall of the semiconductor layer and the insulating layer so that a part of a surface
of the insulating layer is exposed;
etching the insulating layer by an isotropic etching method to expose a surface of the semiconductor substrate; and
growing a single-crystalline layer from the surface of the semiconductor substrate.
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