US 7,521,288 B2
Stacked chip semiconductor device and method for manufacturing the same
Yoshiyuki Arai, Nagaokakyo (Japan); Takashi Yui, Otsu (Japan); Fumito Itou, Ibaraki (Japan); Yasutake Yaguchi, Takatsuki (Japan); and Toshitaka Akahoshi, Takatsuki (Japan)
Assigned to Panasonic Corporation, Osaka (Japan)
Filed on Mar. 14, 2007, as Appl. No. 11/717,953.
Application 11/717953 is a division of application No. 10/881044, filed on Jun. 30, 2004, granted, now 7,239,021.
Claims priority of application No. 2003-192139 (JP), filed on Jul. 04, 2003.
Prior Publication US 2007/0187811 A1, Aug. 16, 2007
Int. Cl. H01L 21/00 (2006.01)
U.S. Cl. 438—109  [438/118; 257/E21.503; 257/E21.511] 6 Claims
OG exemplary drawing
 
1. A method for manufacturing a stacked chip semiconductor device, comprising:
flip-chip mounting a first semiconductor chip having electrode pads to a substrate;
injecting an adhesive into a gap between the substrate and the first semiconductor chip so as to form a first adhesive layer of the adhesive with a fringe protruding from an edge of the first semiconductor chip to form a fillet;
bonding a second semiconductor chip on an upper part of the first semiconductor chip via a second adhesive layer;
connecting electrode pads of the second semiconductor chip and the electrode pads of the substrate via wires; and
encapsulating the first semiconductor chip, the second semiconductor chip and the wires with a molded resin, wherein
in the flip-chip mounting, the first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side from which the adhesive is injected in the underfilling.