| US 7,521,283 B2 | ||
| Manufacturing method of chip integrated substrate | ||
| Yoshihiro Machida, Nagano (Japan); and Takaharu Yamano, Nagano (Japan) | ||
| Assigned to Shinko Electric Industries Co., Ltd., Nagano (Japan) | ||
| Filed on Oct. 25, 2005, as Appl. No. 11/257,717. | ||
| Claims priority of application No. 2004-354172 (JP), filed on Dec. 07, 2004. | ||
| Prior Publication US 2006/0121718 A1, Jun. 08, 2006 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—106 [438/108; 438/109; 438/127; 257/E23.001] | 10 Claims |
| 1. A manufacturing method of a chip integrated substrate in which a semiconductor chip is integrated, comprising:
a first step that forms a wiring structure to be connected to the semiconductor chip on a first core substrate;
a second step that disposes the semiconductor chip on a second core substrate; and
a third step that bonds the first core substrate on which the wiring structure is formed to the second core substrate on which
the semiconductor chip is disposed,
wherein the first step includes:
a conductive-layer forming step that forms conductive layers on the first core substrate; and
a plug-wiring forming step that forms a plurality of plug wirings on one of the conductive layers,
wherein the plurality of plug wirings, formed on said one of the conductive layers in the plug-wiring forming step of the
first step, include first plug wirings which are connected to electrode pads of the semiconductor chip and second plug wirings
which are connected to outside terminals.
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