| US 7,519,932 B2 | ||
| System and method for analyzing crosstalk occurring in a semiconductor integrated circuit | ||
| Toshiyuki Sakamoto, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 30, 2006, as Appl. No. 11/393,074. | ||
| Claims priority of application No. P2005-111031 (JP), filed on Apr. 07, 2005. | ||
| Prior Publication US 2006/0230374 A1, Oct. 12, 2006 | ||
| Int. Cl. G06F 9/45 (2006.01); G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—6 [716/4; 716/5] | 6 Claims |
| 1. A system for analyzing crosstalk occurring in a semiconductor integrated circuit, comprising:
a calculator configured to calculate timing windows of first and second wires, which are routed in the semiconductor integrated
circuit, under a first analysis condition and calculate timing windows of the first and second wires under a second analysis
condition;
a sequence determination module configured to determine whether a sequence of the timing windows of the first and second wires
under the first analysis condition interchanges with a sequence of the timing windows of the first and second wires under
the second analysis condition when there is no overlapping of the timing windows under any of the first and second analysis
conditions; and
an analysis module configured to analyze crosstalk occurring between the first and second wires when there is no overlapping
of the timing windows under any of the first and second analysis conditions, the interchange of the sequence of the timing
windows of the first and second wires occurs and when there is an overlapping of the timing windows of the first and second
wires under at least one of the first and second analysis conditions, wherein the analysis module does not analyze the crosstalk
when there is no overlapping of the timing windows under any of the first and second analysis conditions and the interchange
of the sequence of the timing windows does not occur.
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