| US 7,519,790 B2 | ||
| Method, apparatus and system for memory instructions in processors with embedded memory controllers | ||
| Steven R. Carbonari, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Nov. 14, 2005, as Appl. No. 11/274,686. | ||
| Prior Publication US 2007/0113040 A1, May 17, 2007 | ||
| Int. Cl. G06F 12/12 (2006.01) | ||
| U.S. Cl. 711—170 | 6 Claims |
| 4. A processor comprising:
a computing unit;
an input/output (I/O) interface;
a memory interface; and
a memory agent, wherein the memory agent to perform reliability, availability, serviceability (RAS) operations by invoking
one or more native processor instructions dedicated to configuring memory from an operating system without BIOS intervention.
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