| US 7,519,789 B1 | ||
| Method and system for dynamically selecting a clock edge for read data recovery | ||
| Robert L. Macomber, Portland, Me. (US); and David J. Fensore, New Gloucester, Me. (US) | ||
| Assigned to National Semiconductor Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jan. 20, 2005, as Appl. No. 11/39,366. | ||
| Int. Cl. G06F 1/26 (2006.01); H03K 5/19 (2006.01); G11C 7/00 (2006.01) | ||
| U.S. Cl. 711—167 [327/24; 365/221] | 20 Claims |
| 1. A method for dynamically selecting a clock edge for recovering read data, comprising:
determining whether an internal clock signal is high when a first bit of read data is received; and
selecting either a falling edge or a rising edge of the internal clock signal for recovering the read data based on the determination
of whether the internal clock signal is high when the first bit of read data is received;
wherein selecting either the falling edge or the rising edge of the internal clock signal comprises (i) selecting one of the
falling edge and the rising edge of the internal clock signal in response to determining that the internal clock signal is
high when the first bit of read data is received and (ii) selecting another of the falling edge and the rising edge of the
internal clock signal in response to determining that the internal clock signal is not high when the first bit of read data
is received.
|