| US 7,519,755 B2 | ||
| Combined command and response on-chip data interface for a computer system chipset | ||
| Thomas Kunjan, Dresden (Germany); Joerg Winkler, Ullersdorf (Germany); and Frank Barth, Radebeul (Germany) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Oct. 14, 2004, as Appl. No. 10/964,884. | ||
| Claims priority of application No. 10 2004 031 715 (DE), filed on Jun. 30, 2004. | ||
| Prior Publication US 2006/0015667 A1, Jan. 19, 2006 | ||
| Int. Cl. G06F 13/00 (2006.01) | ||
| U.S. Cl. 710—112 | 59 Claims |
| 1. An integrated circuit chip comprising a first and a second circuit unit, wherein:
each of said first and second circuit units are capable of sending requests to the other one of said first and second circuit
units;
each of said first and second circuit units are further capable of sending back a response when receiving a request that requires
a response; and
said first circuit unit is connected to said second circuit unit to send to said second circuit unit request data relating
to a request to be sent by said first circuit unit and response data relating to a response to be sent by said first circuit
unit over a shared signal line, wherein one of said first circuit and said second circuit is capable of buffering said request
data, and wherein the other one of said first circuit and said second circuit is not capable of buffering said request data.
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