| US 7,519,742 B2 | ||
| Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission | ||
| Tomohisa Takai, Kawasaki (Japan); and Ryo Fukuda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 07, 2006, as Appl. No. 11/368,495. | ||
| Application 11/368495 is a continuation of application No. PCT/JP2005/014376, filed on Jul. 29, 2005. | ||
| Claims priority of application No. 2004-222118 (JP), filed on Jul. 29, 2004. | ||
| Prior Publication US 2006/0200591 A1, Sep. 07, 2006 | ||
| Int. Cl. G06F 3/00 (2006.01) | ||
| U.S. Cl. 710—10 [710/61; 710/118] | 12 Claims |
| 1. A semiconductor integrated circuit apparatus, comprising:
a data transmitter circuit having a shift register which stores identification number data and transfer data, and a transmission
control circuit having a first data converter circuit which converts each of the bits of the identification number data and
transfer data to 2-bit complementary data, and outputs the 2-bit complementary data to first and second output terminals,
and a transfer managing circuit which outputs a transfer completion signal to a third output terminal, following transfer
of the identification number data, the transfer managing circuit including a unit configured to output the transfer completion
signal in response to a termination of the transfer of the identification number data, and a switching unit configured to
switch a transmission of the identification number data to a transmission of the transfer data in response to the transfer
completion signal;
first, second, and third transmission lines connected to the first, second, and third output terminals, respectively; and
a plurality of data receiver circuits each of which includes a second data converter circuit which restores 2-bit complementary
data transferred from the data transmitter circuit via the first and second transmission lines to the identification number
data and transfer data, a reception control circuit which has an allocated specific identification number, and which, when
the transfer completion signal has been received via the third transmission line, compares the allocated specific identification
number with the identification number data restored by the second data converter circuit, and a shift register provided in
association with the reception control circuit;
wherein the each reception control circuit feeds transfer data transmitted from the data transmitter circuit to the associated
shift register in accordance with a result of comparison between the identification number data and the allocated identification
number.
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