| US 7,519,649 B2 | ||
| System and method for performing decimal division | ||
| Steven R. Carlough, Poughkeepsie, N.Y. (US); Paulomi Kadakia, Bridgeville, Pa. (US); Wen H. Li, Poughkeepsie, N.Y. (US); and Eric M. Schwarz, Gardiner, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Feb. 10, 2005, as Appl. No. 11/55,221. | ||
| Prior Publication US 2006/0179102 A1, Aug. 10, 2006 | ||
| Int. Cl. G06F 7/496 (2006.01) | ||
| U.S. Cl. 708—651 | 9 Claims |
| 1. A system for performing decimal division, the system comprising:
input registers for storing a scaled divisor and a scaled dividend;
a plurality of multiples registers for storing a subset of multiples of the scaled divisor; and
a pipeline mechanism including a two cycle adder, a latching multiplexer connected to the multiples registers and the two
cycle adder, a remainder register connected to the two cycle adder, remainder selection circuitry connected to the remainder
register, quotient selection circuitry connected to the multiplexer, the remainder selection circuitry and the remainder register,
and a quotient accumulator connected to the two cycle adder, the pipeline mechanism calculating quotient digits in response
to the scaled divisor and the scaled dividend, wherein each quotient digit is calculated in three clock cycles and the calculating
includes:
selecting a new quotient digit; and
calculating a new remainder using the two cycle adder, wherein input to the two cycle adder includes data from one or more
of the multiples registers.
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