| US 7,519,642 B2 | ||
| Parallel computation structures to enhance signal-quality, using arithmetic or statistical averaging | ||
| Chester Carroll, 20665 Senator Claude Pepper Dr., Camp Hill, Ala. 36850 (US) | ||
| Filed on Jun. 23, 2008, as Appl. No. 12/144,152. | ||
| Application 12/144152 is a continuation in part of application No. 11/624211, filed on Jan. 17, 2007. | ||
| Claims priority of provisional application 61/035175, filed on Mar. 10, 2008. | ||
| Prior Publication US 2008/0281891 A1, Nov. 13, 2008 | ||
| Int. Cl. G06F 7/38 (2006.01) | ||
| U.S. Cl. 708—445 | 9 Claims |
| 7. An averaging circuit comprising:
a cell array laid out to have m columns and n rows, with each cell configured to hold a single bit value, wherein n and m
are integer numbers;
logic associated with each of the m columns to average n samples that are clocked into the n rows of each of the m column,
the logic comprising:
a first-level counter configured to generate a plurality of output bits representative of a summation or count of the n bit
values in the cell rows of a corresponding cell column;
a second-level logic circuit coupled to the output bits of the first-level counter and configured to generate a plurality
of output bits based on the output bits of the first-level counter, wherein the number of output bits of the second-level
counter is fewer than the number of output bits of the first-level counter; and
a full adder stage coupled to the output bits of the second-level logic circuit and configured to complete an arithmetic average
of all cell values in the n rows of the corresponding column.
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