| US 7,519,137 B2 | ||
| Timing recovery in data communication circuits | ||
| Carl Damien Murray, Dublin (Ireland); Philip Curran, Dublin (Ireland); and Alberto Molina Navarro, Madrid (Spain) | ||
| Assigned to Agere Systems, Inc., Allentown, Pa. (US) | ||
| Filed on Jul. 31, 2002, as Appl. No. 10/207,883. | ||
| Claims priority of provisional application 60/309164, filed on Aug. 02, 2001. | ||
| Prior Publication US 2003/0026369 A1, Feb. 06, 2003 | ||
| Int. Cl. H04L 7/00 (2006.01) | ||
| U.S. Cl. 375—355 [375/229; 375/233; 375/376] | 9 Claims |
| 1. A timing recovery circuit for a data communication transceiver, the timing recovery circuit comprising:
a timing error detector (TED) providing an input to an oscillator via a loop filter, said timing error detector (TED) configured
to perform both decision directed (DD) and non decision directed (NDD) recovery;
an analog to digital converter (ADC) connected directly to and upstream of said TED, said ADC providing an input to said TED
during both NDD and DD recovery;
a feed forward equalizer (FFE) also connected directly to said ADC and receiving an input from said ADC;
the direct connection between said ADC and said TED being upstream of said FFE such that said TED and the input received by
said TED from said ADC are not affected by said FFE, said ADC input being an only input to said TED for NDD recovery;
a decision device connected to and downstream of said FFE, said decision device providing an input to said TED only for DD
recovery such that, during DD recovery, said TED is configured to selectively receive both said ADC input and said decision
device input; and
a switching mechanism configured to connect and disconnect the output of said decision device from said TED for DD recovery
and NDD recovery, respectively.
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