a NOR architecture memory cell array having a plurality of memory cells arranged in an array having m rows and n columns, m and n being positive integers;

m word lines respectively corresponding to the m rows of memory cells, wherein each of the word lines is coupled to n gates of the corresponding row of memory cells;

a row decoder for selecting one of the word lines as a target word line; and

a control circuit, which is coupled to the row decoder, applies an initial enable voltage to the target word line to charge the target word line, and then switches the initial enable voltage to a target voltage after a pre-charge time to make the target word line be charged to the target voltage, wherein the initial enable voltage is higher than the target voltage.