| US 7,518,922 B2 | ||
| NAND type flash memory | ||
| Hiroshi Maejima, Tokyo (Japan); Katsuaki Isobe, Yokohama (Japan); Takumi Abe, Yokohama (Japan); and Ken Takeuchi, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 16, 2007, as Appl. No. 11/749,214. | ||
| Claims priority of application No. 2006-139280 (JP), filed on May 18, 2006. | ||
| Prior Publication US 2007/0280031 A1, Dec. 06, 2007 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.33; 365/227] | 21 Claims |
| 21. A memory device comprising:
a NAND type flash memory provided with a memory cell array wherein a plurality of electronically rewritable memory cells are
placed in a matrix form;
a sense amplifier circuit provided with a plurality of sense amplifiers;
a controller which controls the NAND type flash memory device; and the controller having a data inversion control section
which calculates a exclusive OR of a data couple of adjacent even and odd pages of the memory cell array and inverts the polarity
of the data of the odd page or the even page so that the number of adjacent “1” data and “0” data becomes fewer.
|