| US 7,518,903 B2 | ||
| Semiconductor memory device and semiconductor integrated circuit system | ||
| Masanori Shirahama, Shiga (Japan); Yasuhiro Agata, Osaka (Japan); Yasue Yamamoto, Osaka (Japan); and Hirohito Kikukawa, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Mar. 01, 2007, as Appl. No. 11/712,480. | ||
| Claims priority of application No. 2006-055110 (JP), filed on Mar. 01, 2006. | ||
| Prior Publication US 2007/0206403 A1, Sep. 06, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/189.09; 365/203] | 12 Claims |
| 7. A semiconductor memory device, comprising:
a resistance change memory device with a first node and a second node, for performing a set operation for data and a reset
operation for the data by application of a forward bias voltage and a reverse bias voltage across the first and second nodes;
a first selection line connected with the first node of the resistance change memory device;
a second selection line connected with the second node of the resistance change memory device;
a sense amplifier for amplifying a potential difference between a set reference potential and a potential produced by the
value of resistance of the resistance change memory device;
an amplification control circuit for making the sense amplifier constantly perform amplification operation when the data is
written; and
a write circuit for, at the time of the set operation for writing the data or the reset operation for the written data, starting
the data set operation or the data reset operation in the resistance change memory device, and receiving an output signal
from the sense amplifier to stop the data set operation or the data reset operation according to the received output signal.
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