| US 7,518,901 B2 | ||
| Ferroelectric semiconductor memory device and method for reading the same | ||
| Hidehiro Shiga, Kamakura (Japan); and Daisaburo Takashima, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 24, 2007, as Appl. No. 11/877,890. | ||
| Claims priority of application No. 2006-289973 (JP), filed on Oct. 25, 2006. | ||
| Prior Publication US 2008/0101107 A1, May 01, 2008 | ||
| Int. Cl. G11C 11/22 (2006.01); G11C 11/24 (2006.01) | ||
| U.S. Cl. 365—145 [365/149] | 11 Claims |
| 1. A ferroelectric semiconductor memory device comprising:
a first ferroelectric memory cell and a second ferroelectric memory cell, the memory cells together storing one set of information,
each memory cell comprising a ferroelectric capacitor for holding a charge and a transistor connected in parallel to the ferroelectric
capacitor;
a word-line shared by the first and second ferroelectric memory cells;
a first plate line connected to the first ferroelectric memory cell;
a second plate line connected to the second ferroelectric memory cell;
a selection transistor having one end connected to both the first and second ferroelectric memory cells and another end connected
to a bit-line; and
a control circuit controlling voltages applied to a gate of the selection transistor, the first plate line, the second plate
line, the word-line, and the bit-line.
|