| US 7,518,405 B2 | ||
| Impedance matching circuit, input-output circuit and semiconductor test apparatus | ||
| Shoji Kojima, Tokyo (Japan) | ||
| Assigned to Advantest Corp., Tokyo (Japan) | ||
| Filed on Oct. 09, 2007, as Appl. No. 11/973,547. | ||
| Application 11/973547 is a continuation of application No. 11/326182, filed on Jan. 05, 2006, granted, now 7,317,336. | ||
| Claims priority of application No. 2005-002098 (JP), filed on Jan. 07, 2005. | ||
| Prior Publication US 2008/0186050 A1, Aug. 07, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—82 [326/30] | 7 Claims |
| 1. An impedance matching circuit having:
a first resistance;
a first analog computing unit which multiplies a voltage at one end of the first resistance by a predetermined number, subtracts
a voltage at the other end of the first resistance from the voltage multiplied by the predetermined number, and outputs a
voltage obtained by the subtraction;
a second resistance connected to an output side of the first analog computing unit; and
a second analog computing unit which multiplies a voltage at one end of the second resistance by a predetermined number, subtracts
a voltage at the other end of the second resistance from the voltage multiplied by the predetermined number, and outputs a
voltage obtained by the subtraction,
wherein the first resistance is connected to an output side of the second analog computing unit.
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