| US 7,518,241 B2 | ||
| Wafer structure with a multi-layer barrier in an UBM layer network device with power supply | ||
| Li-Cheng Tai, Kaohsiung (Taiwan); Jui-I Yu, Kaohsiung (Taiwan); Jiunn Chen, Kaohsiung (Taiwan); Chueh-An Hsieh, Kaohsiung (Taiwan); Shyh-Ing Wu, Kaohsiung (Taiwan); Shih-Kuang Chen, Kaohsiung (Taiwan); Tsung-Chieh Ho, Kaohsiung (Taiwan); and Tsung-Hua Wu, Kaohsiung (Taiwan) | ||
| Assigned to Advanced Semiconductor Engineering Inc., Kaohsiung (Taiwan) | ||
| Filed on Aug. 31, 2006, as Appl. No. 11/513,142. | ||
| Claims priority of application No. 94129912 A (TW), filed on Aug. 31, 2005. | ||
| Prior Publication US 2007/0045848 A1, Mar. 01, 2007 | ||
| Int. Cl. H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—738 [257/773; 257/775; 257/780; 257/E23.021; 257/E23.069] | 14 Claims |
| 1. A wafer structure, comprising:
a semiconductor substrate having an active surface, wherein the semiconductor substrate has a plurality of bonding pads positioned
on the active surface and a passivation layer, which covers the active surface exposes the bonding pads;
a plurality of UBM layers disposed on the bonding pads, wherein each of the UBM layers comprises:
an adhesive layer disposed on the bonding pads;
a super-lattice barrier layer disposed on the adhesive layer, wherein the super-lattice barrier layer comprises a plurality
of alternately stacked sub-barrier layers and sub-wetting layers;
a welling layer disposed on the super-lattice barrier layer; and
a plurality of bumps disposed on the wetting layer,
wherein the thickness of the welling layer is Y1, the overall thickness of the sub-wetting layers adds up to Y2, and the quotient of Y1/Y2 ranges between 1 and 2.
|