| US 7,518,229 B2 | ||
| Versatile Si-based packaging with integrated passive components for mmWave applications | ||
| John Michael Cotte, New Fairfield, Conn. (US); Brian Paul Gaucher, New Milford, Conn. (US); Janusz Grzyb, Pfaffikon (Switzerland); Nils Deneke Hoivik, Pleasantville, N.Y. (US); Christopher Vincent Jahnes, Upper Saddle River, N.J. (US); John Ulrich Knickerbocker, Monroe, N.Y. (US); Duixian Liu, Scarsdale, N.Y. (US); John Harold Magerlein, Yorktown Heights, N.Y. (US); Chirag Suryakant Patel, Peekskill, N.Y. (US); Ullrich R. Pfeiffer, Yorktown Heights, N.Y. (US); and Cornelia Kang-I Tsang, Mohegan Lake, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Aug. 03, 2006, as Appl. No. 11/498,689. | ||
| Prior Publication US 2008/0029886 A1, Feb. 07, 2008 | ||
| Int. Cl. H01L 23/04 (2006.01) | ||
| U.S. Cl. 257—698 [257/685; 257/723; 257/724; 257/728; 257/E25.005; 257/E25.01; 257/E25.011; 257/E25.012; 257/E25.029] | 3 Claims |

| 1. An apparatus comprising:
an interposer comprising:
a substrate having an upper surface and a lower surface;
a plurality of cavities formed in the upper surface of said interposer; and
conducting through vias from said upper surface to said lower surface, said conducting through vias at said lower surface
adapted for coupling to a source of electrical signals and a voltage supply;
an antenna structure embedded in a first of said plurality of cavities;
a flip-chip mounted radio frequency integrated circuit chip embedded in a second of said plurality of cavities;
a top Si part comprising:
an upper layer of high-resistivity Si;
a lower dielectric layer;
a plurality of interconnection wirings formed within said lower dielectric layer;
first pads for electrically connecting said integrated circuit chip to said plurality of interconnection wirings, said first
pads comprising micro bumps; and
second pads for connecting said through vias to said plurality of interconnection wirings; and
a micro electro mechanical device positioned on said top Si part and coupled between said integrated circuit and said antenna
structure,
wherein said top Si part is mated with said interposer,
wherein said interposer and said top Si part are bonded together to form a perimeter seal around at least said integrated
circuit chip,
wherein each of said plurality of cavities has a bottom surface coated with Cu and a plurality of sidewalls coated with Cu,
wherein said integrated circuit chip is capable of receiving RF electrical signals with frequencies in a range from 1 to 100
GHz,
wherein said interposer is selected from the group consisting of Si and quartz,
wherein a thermal coefficient of expansion of said top Si part matches a thermal coefficient of expansion of said interposer,
wherein said antenna comprises two spaced apart electrodes increasing in space therebetween from one end to the other to provide
antenna signal propagation away from said spaced apart electrodes where said spacing is greatest in the plane of said electrodes,
wherein said perimeter seal is a metal to metal hermetic seal, and
wherein said perimeter seal extends around the edge of said upper surface of said interposer.
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