| US 7,518,218 B2 | ||
| Total ionizing dose suppression transistor architecture | ||
| Harry N. Gardner, Colorado Springs, Colo. (US) | ||
| Assigned to Aeroflex Colorado Springs, Inc., Colorado Springs, Colo. (US) | ||
| Filed on Mar. 03, 2005, as Appl. No. 11/71,730. | ||
| Prior Publication US 2006/0197108 A1, Sep. 07, 2006 | ||
| Int. Cl. H01L 23/552 (2006.01) | ||
| U.S. Cl. 257—659 [257/508; 257/921; 257/E23.114] | 8 Claims |
| 1. A radiation-hardened transistor, comprising:
an active region surrounded by a first oxide layer;
a gate crossing the active region, defining first and second source/drain regions;
a second oxide layer covering the active region and the gate; and
a single metal region directly disposed on a top surface of the second oxide layer overlapping the boundary of the active
region and completely surrounding each of the ends of the gate that extends beyond the border of the active region,
such that negative charge buildup is suppressed during exposure to ionizing radiation.
|