| US 7,518,182 B2 | ||
| DRAM layout with vertical FETs and method of formation | ||
| Todd R. Abbott, Boise, Id. (US); and Homer M. Manning, Eagle, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Jul. 20, 2004, as Appl. No. 10/894,125. | ||
| Prior Publication US 2006/0017088 A1, Jan. 26, 2006 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—329 [257/296; 257/908; 257/E27.084; 257/E29.131] | 21 Claims |
| 1. An integrated circuit structure comprising:
a substrate;
a vertically stacked transistor having first, second and third stacked conductive regions formed within the substrate, the
second region being of a first conductivity type, and the first and third regions being of a second conductivity type, wherein
the second region resides between the first and third regions, the vertically stacked transistor having a first vertical side
and a second vertical side;
a first bit line and a second bit line located below said transistor and below a surface of the substrate, the first bit line
and the second bit line extending in a first direction, the first bit line and the second bit line extending fully below the
first conductive region and in contact with the first conductive region; and
a conductive line positioned on the first vertical side of the transistor to form a gate of the vertically stacked transistor,
the conductive line extending over both the first bit line and the second bit line and in a second direction which is orthogonal
to the first direction.
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