| US 7,517,745 B2 | ||
| Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof | ||
| Hideji Tsujii, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 17, 2006, as Appl. No. 11/377,860. | ||
| Application 11/377860 is a division of application No. 10/885756, filed on Jul. 08, 2004, granted, now 7,042,050. | ||
| Claims priority of application No. 2004-080810 (JP), filed on Mar. 19, 2004. | ||
| Prior Publication US 2006/0160285 A1, Jul. 20, 2006 | ||
| Int. Cl. H01L 21/338 (2006.01) | ||
| U.S. Cl. 438—184 [438/286; 438/303] | 6 Claims |
| 1. A method of manufacturing a semiconductor device comprising:
forming an element isolation film in a major surface of a semiconductor substrate to form an element region;
forming a dummy pattern layer on the semiconductor substrate in a prospective drain region;
forming an offset-spacer material in the element region and on the dummy pattern layer;
etching back the offset-spacer material, thereby forming a first offset-spacer in contact with a side wall of the dummy pattern
layer;
forming a gate insulating film and a gate electrode in contact with a side wall of the first offset-spacer;
doping a dopant by using the gate electrode and the dummy pattern layer as a mask, thereby forming a first source region in
the semiconductor substrate;
removing the dummy pattern layer; and
doping a dopant by using the gate electrode and the first offset-spacer as a mask, thereby forming a first drain region in
the semiconductor substrate.
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