	US 7,517,737 B2
	Structures for and method of silicide formation on memory array and peripheral logic devices
Yi Hung Li, Kaohsiung (Taiwan); Jen Chuan Pan, Kaohsiung (Taiwan); and Jongoh Kim, Hsinchu (Taiwan)
Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan)
Filed on Feb. 07, 2007, as Appl. No. 11/672,150.
Prior Publication US 2008/0185634 A1, Aug. 07, 2008
Int. Cl. H01L 21/335 (2006.01)

U.S. Cl. 438—142 [257/E21.691]

9 Claims

1. A method of fabricating a memory device and peripheral circuitry on a substrate, the method comprising:

forming a multilayer charge trapping structure over a first area of the substrate, the multilayer charge trapping structure having a first thickness, and including a top layer of dielectric, a bottom layer of dielectric and a charge trapping layer or charge trapping layers between the top layer and the bottom layer;

forming a first gate dielectric layer having a second thickness over a second area of the die;

forming a second gate dielectric layer having a third thickness over a third area of the substrate, wherein the third thickness is greater than the second thickness;

depositing and patterning a gate material over the first, second and third areas of the substrate to define word lines in the first area, and transistor gates in the second and third areas;

selectively etching in the third area to reduce the thickness of the second gate dielectric layer in regions adjacent the gates to have a thickness approximating the second thickness;

implanting dopants aligned with the gates in the second and third areas for formation of source and drain regions in the second and third areas through the second and third gate dielectric layers;

depositing a dielectric spacer material over the wordlines and gates in the first, second, and third areas;

etching the dielectric spacer material to form sidewall spacers on the wordlines and gates, and to expose the charge trapping structure in bit line contact regions in the first area, and to expose the first and second dielectric layers in regions adjacent the sidewall spacers in the second and third areas;

implanting dopants aligned with the sidewall spacers for formation of source and drain regions in the second and third areas;

selectively etching the first and second gate dielectric layers to expose the substrate adjacent the sidewall spacers in the second and third areas, and to expose wordlines and gates in the first, second and third areas without exposing the substrate in the bit line contact regions; and

forming a silicide on the exposed substrate over source and drain regions adjacent the sidewall spacers in the second and third areas, and on the wordlines and gates in the first, second and third areas.