| US 7,516,423 B2 | ||
| Method and apparatus for designing electronic circuits using optimization | ||
| Bart De Smedt, Alken (Belgium); Walter Daems, Mortsel (Belgium); Erik Lauwers, Herent (Belgium); Bendt Sorensen, Le Vaud (Switzerland); and Wim Verhaegen, Leuven (Belgium) | ||
| Assigned to Kimotion Technologies, Leuven (Belgium) | ||
| Filed on Jul. 13, 2004, as Appl. No. 10/890,349. | ||
| Prior Publication US 2006/0015829 A1, Jan. 19, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—1 [716/2; 716/7] | 20 Claims |
| 1. A method of designing an electronic circuit using a design process comprising:
formulating an optimization problem, said optimization problem comprising a plurality of design variables relating to said
electronic circuit and defining at least one design objective;
identifying one or more decorrelations between two or more of said design variables, said identifying one or more decorrelations
comprising at least dividing a search space associated with said optimization problem into a plurality of partitions and evaluating
said partitions;
generating, using a computerized system, an optimized solution to said problem using an evolutionary process, said act of
generating based at least in part on said act of identifying; and
using said solution to implement at least a portion of hardware or logic associated with said circuit.
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