| US 7,516,371 B2 | ||
| ECC control apparatus | ||
| Kenji Sakaue, Yokohama (Japan); Hiroshi Sukegawa, Tokyo (Japan); and Hitoshi Tsunoda, Futtsu (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 27, 2004, as Appl. No. 10/787,183. | ||
| Claims priority of application No. 2003-054686 (JP), filed on Feb. 28, 2003; and application No. 2004-016180 (JP), filed on Jan. 23, 2004. | ||
| Prior Publication US 2004/0205418 A1, Oct. 14, 2004 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—52 [714/763] | 22 Claims |
| 1. An ECC (Error Check and Correct) control apparatus to be connected between a host and a memory, comprising:
a data-path circuit which inputs and outputs data to and from the host, and inputs and outputs data to and from the memory;
an enable interface circuit which receives, from the host, a write-enable signal indicating that data is being written to
the memory, and outputs the write-enable signal to the memory;
a detecting circuit which detects a protected-data region and a redundant region of write data input from the host and having
a predetermined data length;
a code-generating circuit which generates an error-correction code for correcting errors in data of the protected-data region;
a code-inserting circuit which inserts the error-correction code in the redundant region; and
a counter which counts pulses that constitute the write-enable signal,
wherein the data-path circuit outputs the write data to the memory in synchronization with a first clock signal generated
from the write-enable signal, and
the enable interface circuit masks the write-enable signal when a number of counted pulses reaches a prescribed number based
on data items of the write data.
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