| US 7,516,349 B2 | ||
| Synchronized memory channels with unidirectional links | ||
| James W. Alexander, Aloha, Oreg. (US); Rajat Agarwal, Beaverton, Oreg. (US); and Pete D. Vogt, Boulder, Colo. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 29, 2005, as Appl. No. 11/323,345. | ||
| Prior Publication US 2007/0156993 A1, Jul. 05, 2007 | ||
| Int. Cl. G06F 1/12 (2006.01); G06F 1/00 (2006.01); G06F 1/04 (2006.01) | ||
| U.S. Cl. 713—400 [713/500; 713/600] | 17 Claims |
| 1. A memory agent comprising:
a first memory channel interface, including unidirectional links;
a second memory channel interface, including unidirectional links;
logic to synchronize a signal processed by the first memory channel interface with a signal processed by the second memory
channel interface, wherein the synchronization logic includes delay logic;
logic to record a round-trip issue-to-response time of the signal processed by the first memory channel interface; and
logic to record another round-trip issue-to-response time of the signal processed by the second memory channel interface,
wherein the delay logic delays the first signal processed by the first memory channel interface relative to the signal processed
by the second memory channel interface in response to the recorded round-trip issue-to-response times.
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