| US 7,516,313 B2 | ||
| Predicting contention in a processor | ||
| Bratin Saha, San Jose, Calif. (US); Matthew C. Merten, Hillsboro, Oreg. (US); Sebastien Hily, Hillsboro, Oreg. (US); David A. Koufaty, Portland, Oreg. (US); and Per Hammarlund, Hillsboro, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 29, 2004, as Appl. No. 11/27,392. | ||
| Prior Publication US 2006/0161738 A1, Jul. 20, 2006 | ||
| Int. Cl. G06F 13/376 (2006.01); G06F 9/38 (2006.01); G06F 13/18 (2006.01) | ||
| U.S. Cl. 712—239 [712/236; 712/237; 710/108; 710/240; 710/107; 710/40; 710/244; 711/150; 711/163] | 31 Claims |
| 1. A system comprising:
a first predictor to predict whether a lock operation is to be contended;
a second predictor to indicate a level of contention in a program;
a first controller to generate a combined prediction based on a result of the first predictor and the second predictor;
control logic to receive the combined prediction and speculatively prefetch a lock variable for the lock operation if the
combined prediction is indicative of no contention; and
a dynamic random access memory (DRAM) coupled to the first predictor and to the second predictor to store the program.
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