US 7,516,307 B2
Processor for computing a packed sum of absolute differences and packed multiply-add
Mohammad A. Abdallah, Folsom, Calif. (US); and Vladimir Pentkovski, Folsom, Calif. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Nov. 06, 2001, as Appl. No. 10/5,728.
Application 10/005728 is a continuation of application No. 09/052904, filed on Mar. 31, 1998, granted, now 6,377,970.
Prior Publication US 2002/0062331 A1, May 23, 2002
Int. Cl. G06F 9/22 (2006.01); G06F 9/302 (2006.01)
U.S. Cl. 712—222  [708/523] 12 Claims
OG exemplary drawing
 
1. A processor comprising:
a decode unit to decode a plurality of packed data instructions including a packed sum of absolute differences (PSAD) instruction having a first format to identify a first set of packed data, and a packed multiply-add (PMAD) instruction having a second format to identify a second set of packed data, said decode unit to initiate a first set of operations on the first set of packed data responsive to decoding the PSAD instruction and to initiate a second set of operations on the second set of parked data responsive to decoding the PMAD instruction, said second set of operations including at least multiplying corresponding packed data elements of the second set of packed data to produce products and summing said products by pairs; and
an execution unit to perform a first operation of the first set of operations initiated by the decode unit and to perform a second operation of the second set of operations initiated by the decode unit.