| US 7,516,303 B2 | ||
| Field programmable gate array and microcontroller system-on-a-chip | ||
| Arunangshu Kundu, San Jose, Calif. (US); Arnold Goldfein, Sunnyvale, Calif. (US); William C. Plants, Sunnyvale, Calif. (US); and David Hightower, Freemont, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Jul. 22, 2005, as Appl. No. 11/187,068. | ||
| Application 11/187068 is a continuation of application No. 10/821533, filed on Apr. 08, 2004, granted, now 7,069,419. | ||
| Application 10/821533 is a continuation of application No. 09/654237, filed on Sep. 02, 2000, granted, now 6,751,723. | ||
| Prior Publication US 2005/0257031 A1, Nov. 17, 2005 | ||
| Int. Cl. G06F 15/00 (2006.01); G06F 15/76 (2006.01) | ||
| U.S. Cl. 712—36 [712/29] | 10 Claims |
| 1. An integrated circuit comprising:
a field programmable gate array (FPGA) core having logic clusters and static random access memory modules, the FPGA core having
programmable routing resources;
a system bus configured to convey signals within the integrated circuit;
a FPGA virtual component interface translator coupled to the FPGA core and to the system bus, the FPGA virtual component interface
translator configured to translate signals from the FPGA core in a first protocol to the system bus in a second protocol,
and from the system bus in the second protocol to the FPGA core in the FPGA core;
a microcontroller coupled to the system bus and to the programmable routing resources;
a microcontroller virtual component interface translator coupled to the microcontroller and the system bus, the microcontroller
virtual component interface translator configured to translate signals from the system bus in the second protocol to the microprocessor
in a third protocol, and from the microprocessor in the third protocol to the system bus in the second protocol;
programmable routing resources coupled to the FPGA core and to the microcontroller and configured to allow a plurality of
programmable connections between the FPGA core and the microcontroller;
a peripheral bus coupled to the system bus through a bridge;
a first dedicated I/O module; and
a first peripheral virtual component interface translator coupled to the first dedicated I/O module through routing resources
and to and the peripheral bus, the first peripheral virtual component interface translator configured to translate signals
from a fourth protocol in the first dedicated I/O module to the second protocol on the system bus; and to translate signals
from the second protocol on the system bus to the fourth protocol in first dedicated I/O module.
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