| 1. A memory controller performing address and data transfer between a CPU and a memory, said memory controller comprising
a circuit that receives from said CPU a first control signal including at least information indicating whether a type of a
bus cycle is a sequential cycle or a nonsequential cycle and performing control of a bus cycle such that when said first control
signal indicates the sequential cycle, an address continuous with an address of an immediately preceding bus cycle is output
to said memory as an address of a current bus cycle, while when said first control signal indicates the nonsequential cycle,
an address unrestricted by an address of an immediately preceding cycle is output to said memory as an address of a current
bus cycle, said memory controller further comprising
a first circuit that on the premise that a bus cycle immediately following a current bus cycle is the sequential cycle, generates
an address having a value continuous with a current address, before the current bus cycle is completed.
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