| US 7,516,276 B2 | ||
| Runtime register allocator | ||
| Kartik Agaram, Austin, Tex. (US); Marc A. Auslander, Millwood, N.Y. (US); and Kemal Ebcioglu, Katonah, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 30, 2007, as Appl. No. 11/929,879. | ||
| Application 11/929879 is a continuation of application No. 10/732656, filed on Dec. 10, 2003, granted, now 7,290,092. | ||
| Prior Publication US 2008/0052470 A1, Feb. 28, 2008 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—128 [711/137] | 11 Claims |
| 1. An apparatus for accessing a storage structure, said apparatus comprising:
arrangement for providing a storage access instruction;
an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction;
an arrangement for extending a storage access instruction with a plurality of predicted register number fields, the predicted
register number fields each containing a predicted register number corresponding to a speculative location of a load/store
operand associated with a storage access instruction, wherein information contained in the plurality of predicted register
number fields comprises:
an associative set number;
a way number within set; and
an offset within line;
an arrangement for speculatively accessing the multiple predicted locations simultaneously within a storage structure with
a storage access instruction extended by said extending arrangement; and
an arrangement for reverting to said arrangement for inputting an address if the load/store operand is found in none of the
speculative locations;
wherein the storage structure is a data cache,
the speculative locations are speculative cache array locations, and
the predicted register number fields contain information to start the speculative access as soon as the instruction is available,
thereby precluding a need to compute and translate load/store addresses.
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