| US 7,516,059 B2 | ||
| Logical simulation device | ||
| Hiroaki Komatsu, Kawasaki (Japan); and Hirofumi Hamamura, Tokyo (Japan) | ||
| Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
| Filed on Jun. 27, 2005, as Appl. No. 11/166,156. | ||
| Application 11/166156 is a continuation of application No. PCT/JP02/13823, filed on Dec. 27, 2002. | ||
| Prior Publication US 2005/0240388 A1, Oct. 27, 2005 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 703—14 | 9 Claims |
| 1. A logical simulation device executing cycle-based logical simulation using level sort and compile methods, comprising:
a first plurality of processors for performing both an evaluation process of executing simulation of logical blocks using
logical blocks corresponding to one or more gates as an evaluation unit, and a communication process with a remainder of the
first plurality of processors;
a small-capacity data storage unit equivalent to cache memory, and wherein
each of the first plurality of said processors are divided into processor groups composed of a second plurality of processors,
a plurality of the processor groups are connected to each other in a tree-shape hierarchy to constitute one cluster, and
said logical simulation device is composed of a plurality of the clusters; and a trace data storage unit for storing trace
data of the cycle-based logical simulation and an external input signal pattern according to each processor group belonging
to a lower side of the tree-shaped hierarchy.
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