| US 7,516,037 B2 | ||
| Method evaluating threshold level of a data cell in a memory device | ||
| David John Baldwin, Allen, Tex. (US); Eric Blackall, Dallas, Tex. (US); Joseph Devore, Richardson, Tex. (US); and Ross E. Teggatz, McKinney, Tex. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on May 31, 2007, as Appl. No. 11/755,891. | ||
| Application 11/755891 is a division of application No. 11/139172, filed on May 28, 2005, granted, now 7,269,528. | ||
| Prior Publication US 2007/0240026 A1, Oct. 11, 2007 | ||
| Int. Cl. G06F 15/00 (2006.01) | ||
| U.S. Cl. 702—117 [714/7; 714/8; 714/42; 714/54; 700/5; 324/500; 324/512; 324/522; 324/523; 324/537; 324/765; 324/769] | 1 Claim |
| 1. A method for evaluating a memory storage device, comprising the steps of:
applying a low READ signal to the memory storage device;
while applying said low READ signal to the memory storage device, applying a “0” to a programming node of the memory storage
device;
while applying the “0” to a programming node of the memory storage device, applying a high READ signal to the memory storage
device and measuring a first output voltage of the memory storage device;
applying the low READ signal to the memory storage device;
while applying said low READ signal to the memory storage device, applying a test signal to a programming node of the memory
storage device, said test signal being less than a designed threshold level;
while applying the test signal to a programming node of the memory storage device, applying the high READ signal to the memory
storage device and measuring a second output voltage of the memory storage device;
comparing said first output voltage to said second output voltage, wherein a difference between said first output voltage
to said second output voltage less than a predetermined amount indicates proper configuration of the memory storage device.
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