| US 7,515,496 B2 | ||
| Self-refresh timer circuit and method of adjusting self-refresh timer period | ||
| Yoshinori Matsui, Tokyo (Japan); Hitoshi Tanaka, Tokyo (Japan); Kazuhiko Kajigaya, Tokyo (Japan); Akiyoshi Yamamoto, Tokyo (Japan); and Tadashi Onodera, Tokyo (Japan) | ||
| Assigned to Elpida Memory Inc., Tokyo (Japan) | ||
| Filed on Nov. 16, 2007, as Appl. No. 11/984,352. | ||
| Application 11/984352 is a division of application No. 11/297646, filed on Dec. 09, 2005, granted, now 7,307,909. | ||
| Claims priority of application No. 2004-359233 (JP), filed on Dec. 10, 2004. | ||
| Prior Publication US 2008/0074940 A1, Mar. 27, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—222 [365/233.1; 331/69; 331/70; 331/176] | 12 Claims |
| 1. A semiconductor device having a timer circuit comprising:
a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic;
a control current generating circuit for applying an output voltage of said temperature- dependent voltage source to a temperature
detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a
current flowing through said temperature detecting device;
a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of said control current;
and
an adjusting circuit including a first adjusting circuit for adjusting coefficient of powers of temperatures in a temperature
characteristic of said timer period and a second adjusting circuit for adjusting logarithmic level of the temperature characteristic
of said timer period.
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